Method for manufacturing tft array substrate of liquid crystal display device

ABSTRACT

A semiconductor layer protruding beside a source line is removed in order to increase aperture ratio, decrease resistance of the source line and prevent source-common capacitance from increasing. When a part of a passivation film is removed to form a contact hole, the passivation film on the source line, the passivation film beside the source line and a gate insulating layer beside the source line are simultaneously removed. A portion protruding beside the source line is removed from thus exposed semiconductor layer using a resist pattern for removing the part of the passivation film and/or the source line as a mask.

TECHNICAL FIELD

[0001] The present invention relates to a method for manufacturing aliquid crystal display device, and more particularly to a method ofmanufacturing a TFT array substrate of an active matrix liquid crystaldisplay.

BACKGROUND ART

[0002] In a liquid crystal display, an electro-optic characteristic of aliquid crystal is utilized and combined with a polarizing plate in orderto carry out display by controlling a voltage to be applied to theliquid crystal. A liquid crystal display has a light weight than that ofa CRT and is excellent in portability, so that has been applied to adisplay device of a mobile computer in recent years.

[0003] In particular, an active matrix liquid crystal display, in whicha switching element such as a thin film transistor (TFT) is provided foreach pixel to control a voltage to be applied to a liquid crystal, ischaracterized by a higher display quality as compared with a simplematrix type liquid crystal display, and has vigorously been developedand applied.

[0004]FIG. 1 shows an equivalent circuit of a basic active matrix typeliquid crystal display, and an operation thereof will be described. FIG.1(b) is a partially enlarged view showing a P portion of FIG. 1(a).

[0005] A switching element 7 such as a TFT, a liquid crystal capacitance(capacitance of liquid crystal in the pixel) 8 and an auxiliarycapacitance 9 are formed to define a pixel in the intersecting portionof a gate line 1 and a source line 2. The pixels are arranged in amatrix to form a TFT array substrate.

[0006] When a selection pulse is applied to the gate line, all of theswitching elements connected to the gate line are turned ON and a signalapplied to a source line connected to each switching element is writtento the liquid crystal capacitance and the auxiliary capacitance throughthe switching element. When the application of the selection pulse iscompleted and the gate line is brought into a non-selection state, theswitching elements are turned OFF so that electric charges written tothe liquid crystal capacitance and the auxiliary capacitance are helduntil one vertical scanning period passes and the selection pulse isapplied again to the gate line.

[0007] In the active matrix type liquid crystal display, usually, aswitching element such as a TFT is provided on one of two substrates toform a TFT array substrate, a common electrode is provided on the othersubstrate to form a counter substrate, and the two substrates areopposed to each other interposing a liquid crystal layer therebetween.

[0008] A method for manufacturing a TFT array substrate according to theconventional art will be described with reference to FIGS. 2, 3 and 4.

[0009]FIG. 2 is an enlarged plane view showing the main part of the TFTarray substrate. In FIG. 2, a TFT comprising a gate electrode 12, asource electrode 21 and a drain electrode 22 is formed in theintersecting portion of a gate line 13 and a source line 20, and thedrain electrode 22 of the TFT is connected to a pixel electrode 27through a contact hole 24. In order to apply a selection pulse from theoutside, the end of the gate line 13 is extended to the outside of adisplay region of the liquid crystal display to form a lower pad 15. Thelower pad 15 is connected to an upper pad 28 through a contact hole 25,and the selection pulse is inputted from the upper pad.

[0010] The end of the gate line 20 is also extended to the outside ofthe display region of the liquid crystal display to form a lower pad 23,which is not shown in FIG. 2. The lower pad 23 is connected to an upperpad 29 through a contact hole 26, and a signal is inputted from theupper pad.

[0011] The reference numeral 14 in FIG. 2 denotes a common line forforming an auxiliary capacitance together with a pixel electrode 27.Moreover, the reference numeral 38 denotes a channel of the TFT.

[0012]FIGS. 3 and 4 are sectional views illustrating the method formanufacturing a TFT array substrate in FIG. 2.

[0013] First of all, a first metal layer is formed on an insulatingsubstrate 11 by using a method such as sputtering. The first metal layercomprises metal such as Cr, Al or Mo, an alloy containing the metal asan essential component, or a laminated layer thereof. Then,photolithography is carried out by using a photoresist, thereby removingan unnecessary portion from the first metal layer by etching or thelike. Thus, a gate electrode 12, a gate line 13, a common line 14 and alower pad 15 are formed. This state is shown in FIG. 3(a).

[0014] Next, an insulating film (a gate insulating film) 16 comprisingSiNx or SiO₂ is formed by various CVD methods such as plasma CVD, or bysputtering, evaporation, coating or the like. Furthermore, an a-Si:Hlayer (a first semiconductor layer) 17, and a semiconductor layer (animpurity semiconductor layer or a second semiconductor layer) 18 such asan n+a-Si:H film or a microcrystal n+Si layer which is doped with animpurity such as phosphorus, antimony or boron are formed by plasma CVD,sputtering or the like. Furthermore, a second metal layer 19 is formedby using sputtering or the like. A second metal layer comprises metalsuch as Cr, Al or Mo, an alloy containing the metal as an essentialcomponent or a laminated layer thereof.

[0015] Subsequently, a photoresist R is applied to form a resist patterncomprising a region A in which the photoresist R has a great thickness,a region B in which the photoresist R has a small thickness, and aregion C in which the photoresist R is removed. This state is shown inFIG. 3(b).

[0016] Next, the second metal layer 19 is subjected to etching by usingthe resist pattern. The second metal layer 19 in the region C having nophotoresist R is selectively removed. This state is shown in FIG. 3(c).

[0017] Then, the photoresist R in the region B is removed. At this time,since the photoresist R in the region A has a great thickness, it is notremoved but remained. This state is shown in FIG. 3(d).

[0018] Next, the photoresist R remaining in the region A is used tofirst etch the semiconductor layers 18 and 17, thereby removing thesemiconductor layers 18 and 17 in the region C, and to then etch thesecond metal layer 19, thereby removing the second metal layer 19 in theregion B. This state is shown in FIGS. 3(e) and 4(a).

[0019] Furthermore, the semiconductor layer 18 in the region B isremoved by etching and the whole resist R is then removed. This state isshown in FIG. 4(b). A source line 20, a source electrode 21, a drainelectrode 22 and a lower pad 23 are formed on a substrate.

[0020] Subsequently, a protective film 35 is formed over the wholesurface and photolithography is then carried out by using thephotoresist or the like, and contact holes 24, 25 and 26 are formed byetching or the like. This state is shown in FIG. 4(c).

[0021] Finally, ITO (Indium Tin Oxide) is formed over the whole surface,the photolithography is carried out by using the photoresist or thelike, and an unnecessary portion is removed by etching to form an ITOpixel electrode 27 and upper pads 28 and 29. This state is shown in FIG.4(d).

[0022] According to the manufacturing method described above, a TFTarray substrate can be manufactured by carrying out the photolithographyfour times in total, that is, by means of four photomasks. Therefore, aprocess can be shortened and a cost can be reduced.

[0023] In the above-mentioned manufacturing method, meanwhile, thesource line 20, the source electrode 21, the drain electrode 22 and thelower pad 23, and the semiconductor layers 18 and 17 which arepositioned thereunder are formed by using the same photoresist R.However, because methods or conditions of the etching are different, anamount of a reduction in the widthwise direction (side etching amount)in the line during the etching of the second metal layer 19 is largerthan the side etching amounts of the semiconductor layers 18 and 17. Asshown in FIGS. 4(a) to 4(d), therefore, the semiconductor layer 18 andthe semiconductor layer 17 are protruded beside the source line 20.

[0024] In general, in the case in which the material of the source line(i.e. the second metal layer 19) is Cr, Al, Mo or the like, the sideetching amount is approximately 0.5 to 1.0 μm on either side. On theother hand, the side etching amounts of the semiconductor layer 18 andthe semiconductor layer 17 are approximately 0 μm. Accordingly, in thecase in which the width of the source line in the photomask to be usedin the photolithography is 10 μm, a source line to be actually formedhas a width of 8 to 9 μm and the semiconductor layer 18 and thesemiconductor layer 17 are protruded by approximately 1 to 2 μm.

[0025] In order to obtain a liquid crystal display in which displayhaving a high luminance can be carried out and a display quality isexcellent, it is desirable that the aperture ratio of a TFT arraysubstrate should be increased as much as possible. In order to preventthe delay of a signal to be applied to the source line 20 and adegredation in a display quality such as an uneven luminance, moreover,it is desirable that the resistance of the source line 20 should bereduced as much as possible.

[0026] If the protrusion of the semiconductor layer 18 and thesemiconductor layer 17 can be removed, the aperture ratio can beenhanced without decreasing the width of the source line 20, that is,without increasing the resistance of the source line 20. In addition, ifthe aperture ratio is equal, the width of the source line 20 can be moreincreased so that the resistance of the source line 20 can be reduced.

[0027] Furthermore, there is also a problem in that the semiconductorlayers 18 and 17 thus protruded form a capacitance together with thecommon electrode of the counter substrate, thereby increasing asource-common capacitance.

[0028] In the method of manufacturing a TFT array substrate using fourphotomasks described above, particularly, the second metal layer 19 (thesource line 20) is exposed to the etching plural times (see FIG. 3(c)and FIG. 4(a)).

[0029] For this reason, the difference between the side etching amountof the source line 20 and the side etching amounts of the semiconductorlayers 18 and 17 is further increased. For example, in the case in whichthe source line in the photomask has a width 10 μm, a source line to beactually formed has a width of approximately 6 to 7 μm and thesemiconductor layers 18 and 17 are protruded by approximately 3 to 4 μm.

[0030] Accordingly, a reduction in the aperture ratio, an increase inthe resistance of the source line and an increase in the source-commoncapacitance have become more serious. Therefore, there has been greatlydesired a manufacturing method capable of removing the protrudedsemiconductor layers 18 and 17.

[0031] It is an object of the present invention to remove asemiconductor layer protruded beside a source line in a process formanufacturing a TFT array of an active matrix liquid crystal displaydevice.

SUMMARY OF INVENTION

[0032] According to the present invention, a gate line, a source line, aTFT element and the like are formed; thereafter a passivation film isthen formed; and the passivation film on the source line, thepassivation film provided beside the source line and a gate insulatingfilm provided beside the source line are simultaneously removed toexpose the source line and a semiconductor layer provided under thesource line when removing a part of the passivation film to form acontact hole.

[0033] Furthermore, a portion in the exposed semiconductor layer whichis protruded besides the source line is removed by using, as a mask, aresist pattern for removing a part of the passivation film and/or asource line.

[0034] Alternatively, a portion in the exposed semiconductor layer whichis protruded beside the source line is removed by using, as a mask, thepassivation film from which a part thereof is removed and/or the sourceline.

[0035] According to another aspect of the present invention, a gateline, a source line, a TFT element and the like are formed and apassivation film is not then formed, and a portion in a semiconductorlayer provided under the exposed source line which is protruded besidethe source line is removed by using the source line as a mask.

[0036] According to still another aspect of the present invention, asemiconductor layer is caused to remain beside the source line whenforming the source line. Consequently, when removing a part of thepassivation film to form a contact hole, only the passivation filmprovided on and beside the source line is removed and a gate insulatingfilm provided beside the source line is not removed.

[0037] Furthermore, a portion in the semiconductor layer exposed by theremoval of the passivation film which is protruded beside the sourceline is removed by using, as a mask, a resist pattern for removing apart of the passivation film and/or the source line.

[0038] Alternatively, a portion in the semiconductor layer exposed bythe removal of the passivation film which is protruded beside the sourceline is removed by using, as a mask, the passivation film from which apart thereof is removed and/or the source line.

[0039] In the present invention, when selectively removing a part of anITO film, the ITO film provided on the source line is not removed butmay be left to cover the source line.

BRIEF DESCRIPTION OF DRAWINGS

[0040]FIG. 1 is a view for explaining the operation of an active matrixliquid crystal display device;

[0041]FIG. 2 is an enlarged plan view showing the main part of a TFTarray substrate;

[0042]FIG. 3 is a sectional view for explaining a method formanufacturing the TFT array substrate in FIG. 2 according to theconventional art;

[0043]FIG. 4 is a sectional view for explaining the method formanufacturing the TFT array substrate in FIG. 2 according to theconventional art, illustrating succeeding steps to FIG. 3;

[0044]FIG. 5 is a sectional view for explaining a method formanufacturing a TFT array substrate according to a first embodiment ofthe present invention;

[0045]FIG. 6 is a sectional view for explaining the method formanufacturing a TFT array substrate according to the first embodiment ofthe present invention, illustrating succeeding steps to FIG. 5;

[0046]FIG. 7 is a sectional view for explaining the method formanufacturing a TFT array substrate according to the first embodiment ofthe present invention, illustrating succeeding steps to FIG. 6;

[0047]FIG. 8 is a sectional view for explaining a method formanufacturing a TFT array substrate according to a second embodiment ofthe present invention;

[0048]FIG. 9 is a sectional view for explaining a method formanufacturing a TFT array substrate according to a third embodiment ofthe present invention;

[0049]FIG. 10 is a sectional view for explaining the method formanufacturing a TFT array substrate according to the third embodiment ofthe present invention, illustrating succeeding steps to FIG. 9;

[0050]FIG. 11 is a sectional view for explaining the method formanufacturing a TFT array substrate according to the third embodiment ofthe present invention, illustrating succeeding steps to FIG. 10;

[0051]FIG. 12 is a sectional view for explaining a method formanufacturing a TFT array substrate according to a fourth embodiment ofthe present invention;

[0052]FIG. 13 is a sectional view for explaining a method formanufacturing a TFT array substrate according to the fourth embodimentof the present invention, illustrating succeeding steps to FIG. 12; and

[0053]FIG. 14 is a sectional view for explaining a method formanufacturing a TFT array substrate according to a fifth embodiment ofthe present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0054] Embodiments of the present invention will be described below withreference to the drawings.

EMBODIMENT 1

[0055] The EMBODIMENT 1 of the present invention will be described withreference to FIGS. 5, 6 and 7. FIGS. 5, 6 and 7 are sectional viewsshowing a TFT array substrate provided with a reverse stagger type TFT,illustrating a manufacturing method therefor.

[0056] The method for manufacturing the TFT array substrate according tothe EMBODIMENT 1 of the present invention includes the following steps.

[0057] (1) First of all, a first metal layer is formed on an insulatingsubstrate 11, photolithography is then carried out by using aphotoresist or the like, an unnecessary portion is removed from thefirst metal layer by etching or the like, and a gate electrode 12, agate line 13, a common line 14 and a lower pad 15 are formed (FIG.5(a)).

[0058] (2) Next, four layers of a gate insulating film 16 comprisingSiNx, SiO₂ or the like, an a-Si layer (an amorphous semiconductor film,a first semiconductor layer) 17, an n+a-Si layer (an amorphous impuritysemiconductor film, a second semiconductor layer) 18 and a second metallayer 19 are formed on the substrate in order to cover the gateelectrode 12, the gate line 13, the common line 14 and the pad 15.

[0059] (3) After a photoresist R is applied, a resist pattern includinga region A in which the photoresist R has a great thickness, a region Bin which the photoresist R has a small thickness, and a region C inwhich the photoresist R is removed is formed using a photomask.

[0060] The region A in which the photoresist R has a great thicknesscorresponds to a region in which the second metal layer 19 is to be leftas a source electrode, a drain electrode, a source line and a drainline, the region C from which the photoresist R is removed correspondsto a region in which at least the second metal layer 19, the secondsemiconductor layer 18 and the first semiconductor layer 17 are to beetched and removed, and the region B in which the photoresist R has asmall thickness corresponds to a region in which the second metal layer19 and the second semiconductor layer 18 are to be removed to form a TFTchannel portion 38 (FIG. 5(b)).

[0061] In the present embodiment, only the TFT channel portion 38 is setto be the region B. Although the region B is not limited to the TFTchannel portion 38, the present invention is characterized in that atleast a portion to be a source line 20 later and a vicinity thereof arenot set to be the region B.

[0062] (4) Next, the second metal layer 19 in the C region is firstremoved by etching (FIG. 5(c)).

[0063] (5) Then, the photoresist R in the region B is removed. At thistime, since the photoresist R in the region A has a great thickness, itis not removed but left (FIG. 5(d)).

[0064] (6) Thereafter, the semiconductor layers 18 and 17 in the regionC are removed by the etching or the like (FIG. 5(e)).

[0065] (7) Furthermore, the second metal layer 19 in the region B isremoved (FIG. 6(a)).

[0066] (8) Subsequently, the second semiconductor layer 18 in the regionB is removed and the whole photoresist R is then removed (FIG. 6(b)).

[0067] The above-described steps are the same as those in theconventional art and the source line 20 comprising the second metallayer 19 has a larger side etching amount as compared with thesemiconductor layer 18 and the semiconductor layer 17 as describedabove. Therefore, the semiconductor layer 18 and the semiconductor layer17 are protruded beside the source line 20.

[0068] (9) After a passivation film 35 is formed on the whole surface ofthe TFT array substrate in this condition, a photoresist is applied anda resist pattern 36 is formed by using a photomask (FIG. 6(c)).

[0069] The resist pattern 36 is used for removing a part of thepassivation film 35 to form contact holes 24, 25 and 26 at a next step,and at the same time, has such a pattern that the passivation film 35 ina region 30, i.e. on the source line 20 and the vicinity thereof, isalso removed.

[0070] (10) By using the resist pattern 36, the passivation film 35 isetched to form a contact hole 24 for electrically connecting a drainelectrode 22 to an ITO pixel electrode 27, a contact hole 25 forelectrically connecting the lower pad 15 to an upper pad 28, and acontact hole 26 for electrically connecting a lower pad 23 to an upperpad 29. At this time, as described above, the passivation film 35 in theregion 30, that is, on the source line 20 and the vicinity thereof, isalso removed, and at the same time, the gate insulating film 16 in theregion 30 is also removed (FIG. 6(d)).

[0071] (11) Next, etching is carried out by using the resist pattern 36and the source line 20 as masks, thereby removing the semiconductorlayers 18 and 17 protruded beside the source line 20, and thereafter theresist pattern 36 is removed (FIG. 7(a)).

[0072] At this time, the resist pattern may be removed earlier and theprotruded semiconductor layers 18 and 17 may be etched by using thepassivation film 35 and the source line 20 as masks.

[0073] Moreover, the second metal layer 19 forming the source line 20 isto be formed of such a material as not to be etched simultaneously withthe etching of the protruded semiconductor layers 18 and 17, forexample, Cr or the like.

[0074] (12) Then, an ITO film is formed over the whole surface andphotolithography is thereafter carried out by using a photoresist or thelike, and patterning for removing an unnecessary portion of the ITO filmis performed by etching, thereby forming an ITO pixel electrode 27 andupper pads 28 and 29 (FIG. 7(b)).

[0075] As described above, according to the present invention, a TFTarray substrate can be manufactured by carrying out the same number ofphotolithography, that is, four times in total as the conventionalmanufacturing method. Therefore, using four photomasks which is the samenumber as that in the conventional manufacturing method, a TFT arraysubstrate can be manufactured and the semiconductor layer 18 and thesemiconductor layer 17 which are protruded beside the source wiring canbe removed.

[0076] Accordingly, higher aperture ratio of the TFT array substrate andlower resistance of the source line can be achieved without increasing atime and cost required for manufacture, and furthermore, it is possibleto eliminate the drawback of the conventional art that a source-commoncapacitance is increased.

EMBODIMENT 2

[0077] The EMBODIMENT 2 of the present invention will be described withreference to FIG. 8.

[0078] The present embodiment is characterized in that a source line 20is covered with an ITO film 37.

[0079] In the EMBODIMENT 1, the source line 20 is exposed as is apparentfrom FIG. 7(b). Accordingly, it is necessary to select a material whichis not reactive to a liquid crystal for the material of the source line20, that is, the second metal layer 19.

[0080] In the present embodiment, an ITO film provided on the sourceline 20 is left through the patterning of the ITO film, thereby formingthe ITO film 37 covering the source line 20 and semiconductor layers 17and 18 positioned under the source line 20.

[0081] Since the ITO film 37 covers the source line 20, a degree offreedom for the selection of the material of the source line 20 (asecond metal layer 19). Furthermore, both the source line 20 and the ITOfilm 37 function as source line. Therefore, the resistance of the sourceline can be reduced. Moreover, even if the source line 20 is broken, theITO film 37 fills a redundant role so that reliability can also beenhanced.

EMBODIMENT 3

[0082] The EMBODIMENT 3 of the present invention will be described withreference to FIGS. 9, 10 and 11. FIGS. 9, 10 and 11 are sectional viewsshowing a TFT array substrate provided with a reverse stagger type TFT,illustrating a manufacturing method therefor.

[0083] In the EMBODIMENT 1, a gate insulating film 16 is also removed ina region 30 in the vicinity of a source line 20 as is apparent from FIG.7(b). Accordingly, in the case in which the source line 20 and a commonline 14 are provided adjacently, there is a possibility that a shortcircuit might be caused between both lines. In the present embodiment,therefore, the gate insulating film 16 is not removed but left in theregion 30 in the vicinity of the source line 20.

[0084] The process will be described below.

[0085] (1) First of all, a first metal layer is formed on an insulatingsubstrate 11 and is then patterned by using photolithography to form agate electrode 12, a gate line 13, a common line 14 and a lower pad 15(FIG. 9(a)).

[0086] (2) Next, four layers of a gate insulating film 16, a firstsemiconductor layer 17, a second semiconductor layer 18 and a secondmetal layer 19 are formed on the substrate in order to cover the gateelectrode 12, the gate line 13, the common line 14 and the pad 15.

[0087] (3) After a photoresist R is applied, a resist pattern includinga region A (A₁) in which the photoresist R has a great thickness, aregion B (B₁) in which the photoresist R has a small thickness, and aregion C in which the photoresist R is removed is formed using aphotomask.

[0088] While only the TFT channel portion is set to be the region B inthe EMBODIMENT 1, the region B₁, in which the photoresist R has a smallthickness is provided also in the vicinity of the region A₁ to be thesource line later in the present embodiment (FIG. 9(b)).

[0089] (4) Next, the second metal layer 19 in the C region is firstremoved by etching or the like (FIG. 9(c)).

[0090] (5) Next, while the photoresist R in the region A (A₁) is left,the photoresist R in the region B (B₁) is removed (FIG. 9(d)).

[0091] (6) Thereafter, the semiconductor layers 18 and 17 in the regionC are removed by etching or the like (FIG. 9(e)).

[0092] (7) Furthermore, the second metal layer 19 in the region B (B₁)is removed (FIG. 10(a)).

[0093] (8) Subsequently, the second semiconductor layer 18 in the regionB (B₁) is removed and the whole photoresist R is then removed (FIG.10(b)).

[0094] As described above, the source line 20 comprising the secondmetal layer 19 has a larger side etching amount as compared with thesecond semiconductor layer 18. Therefore, the semiconductor layer 18 isprotruded beside the source line 20.

[0095] (9) After a passivation film 35 is formed on the whole surface ofthe TFT array substrate in this condition, a photoresist is applied anda resist pattern 36 is formed by using a photomask (FIG. 10(c)).

[0096] The photoresist pattern 36 is used for removing a part of thepassivation film 35 to form contact holes 24, 25 and 26 at a next step,and at the same time, has such a pattern that the passivation film 35 ina region 30 which includes the source line 20 and the vicinity thereofis also removed.

[0097] (10) By using the resist pattern 36, the passivation film 35 isetched to form contact holes 24, 25 and 26. As described above, thepassivation film 35 in the region 30, i.e. on the source line 20 and inthe vicinity thereof, is also removed (FIG. 10(d)).

[0098] (11) Next, etching is carried out by using the resist pattern 36and the source line 20 as masks, thereby removing the semiconductorlayer 18 protruded under the source line 20 and the semiconductor layer17 provided in the vicinity of the source line 20, and then removing theresist pattern (FIG. 11(a)).

[0099] At this time, the resist pattern may be removed earlier and theprotruded semiconductor layer 18 and the semiconductor layer 17 may beetched by using the passivation film 35 and the source line 20 as masks.

[0100] Moreover, the second metal layer 19 forming the source line 20 isto be formed of such a material as not to be etched simultaneously withthe etching of the semiconductor layer 18 and the semiconductor layer17, for example, Cr or the like.

[0101] (12) Then, an ITO film is formed over the whole surface andphotolithography is used to carry out the patterning, thereby forming anITO pixel electrode 27 and upper pads 28 and 29 (FIG. 11(b)).

[0102] As described above, according to the present embodiment, the gateinsulating film 16 provided in the vicinity of the source line 20 is notremoved but left. Therefore, there is no possibility that a shortcircuit might be occurred between the source line 20 and the common line14.

[0103] While the source line 20 is exposed in the present embodiment, itis a matter of course that the source line 20 can be covered with theITO film in the same manner as described in the EMBODIMENT 2.

EMBODIMENT 4

[0104] The EMBODIMENT 4 of the present invention will be described withreference to FIGS. 12 and 13. FIGS. 12 and 13 are sectional viewsshowing a TFT array substrate provided with a reverse stagger type TFT,illustrating a manufacturing method therefor.

[0105] The present embodiment is different from the EMBODIMENT 1 in thatthe passivation film 35 is omitted.

[0106] The process will be described below.

[0107] (1) First of all, a first metal layer is formed on an insulatingsubstrate 11 and is then patterned by using photolithography to form agate electrode 12, a gate line 13, a common line 14 and a lower pad 15(FIG. 12(a)).

[0108] (2) Next, four layers of a gate insulating film 16, a firstsemiconductor layer 17, a second semiconductor layer 18 and a secondmetal layer 19 are formed on the substrate in order to cover the gateelectrode 12, the gate line 13, the common line 14 and the pad 15.

[0109] (3) After a photoresist R is applied, a resist pattern includinga region A in which the photoresist R has a great thickness, a region Bin which the photoresist R has a small thickness, and a region C inwhich the photoresist R is removed is formed (FIG. 12(b)).

[0110] (4) Next, the second metal layer 19 in the region C is firstremoved by etching (FIG. 12(c)).

[0111] (5) Next, while the photoresist R in the region A is left, thephotoresist R in the region B is removed (FIG. 12(d)).

[0112] (6) Thereafter, the semiconductor layers 18 and 17 in the regionC are removed by etching or the like (FIG. 12(e)).

[0113] (7) Furthermore, the second metal layer 19 in the region B isremoved (FIG. 13(a)).

[0114] (8) Subsequently, the second semiconductor layer 18 in the regionB is removed and the whole photoresist R is then removed (FIG. 13(b)).

[0115] The manufacturing steps described above are the same as those inthe EMBODIMENT 1. As described above, the semiconductor layer 18 and thesemiconductor layer 17 are protruded beside the source line 20.

[0116] (9) After a photoresist is applied to the surface of the TFTarray substrate in this condition, and a photomask is used to form aresist pattern. Thus, a contact hole is formed in the gate insulatingfilm 16 provided on the lower pad 15. By etching using the source line20 as a mask, furthermore, the semiconductor layer 18 and thesemiconductor layer 17 which are protruded under the source line 20 areremoved (FIG. 13(c).

[0117] (10) Then, an ITO film is formed over the whole surface andphotolithography is used to carry out the patterning, thereby forming anITO pixel electrode 27 and upper pads 28 and 29. In the presentembodiment, the ITO pixel electrode 27 and the drain electrode 22, andthe upper pad layer 29 and the lower pad 23 are directly provided incontact with each other without using the contact hole (FIG. 13(d)).

[0118] In the EMBODIMENT 1, the passivation film 35 provided in thevicinity of the source line 20 is removed in order to remove thesemiconductor layer 18 and the semiconductor layer 17 which areprotruded beside the source line 20 (FIG. 6(d)). At the same time, thegate insulating layer adjacent to the source line is also removed.Accordingly, in the case in which the source line 20 and the common line14 are provided adjacently, there is a possibility that a short circuitmight be occurred between both lines.

[0119] According to the present embodiment, it is not necessary toremove the passivation film 35. Therefore, the gate insulating film 16provided in the vicinity of the source line 20 is not removed.Accordingly, also in the case in which the source line 20 and the commonline 14 are provided adjacently, there is no possibility that a shortcircuit might be caused between both lines.

[0120] While the source line 20 is exposed in the present embodiment, itis a matter of course that the source line 20 can be covered with theITO film in the same manner as in the EMBODIMENT 2.

[0121] According to the present embodiment, the passivation film 35 isomitted. Therefore, a TFT array substrate can be fabricated at a lowcost in a short time, and the semiconductor layer 18 and thesemiconductor layer 17 which are protruded beside the source line 20 canbe removed. Therefore, an aperture ratio can be enhanced and theresistance of the source line can be reduced, and furthermore, it ispossible to eliminate a drawback that a source-common capacitance isincreased.

EMBODIMENT 5

[0122] The EMBODIMENT 5 of the present invention will be described withreference to FIG. 14. FIG. 14 is a sectional view showing a TFT arraysubstrate provided with a reverse stagger type TFT, illustrating amanufacturing method therefor.

[0123] In the EMBODIMENT 4 described above, the TFT array substrate isfabricated by using four photomasks in total, that is, carrying outphotolithography four times. According to the present embodiment, it ispossible to manufacture a TFT array substrate by using three photomasks,that is, carrying out the photolithography three times.

[0124] In the EMBODIMENT 4, at the step shown in FIG. 13(c), thephotoresist is applied to the surface of the TFT array substrate, thephotomask is used to form the resist pattern, and the contact hole isformed in the gate insulating film 16 provided on the lower pad 15.

[0125] Then, the ITO film is formed over the whole surface and thephotolithography is used to carry out patterning, thereby forming theITO pixel electrode 27 and the upper pads 28 and 29. Accordingly, thelower pad 15 and the upper pad 28 are electrically connected through acontact hole.

[0126] In the present embodiment, in contrast, the gate insulating film16 provided on the lower pad 15 is removed without using the photomaskbefore the ITO film is formed (FIG. 14(a)). The removal is carried outthrough a peripheral exposing step, in which the photoresist in theperipheral portion of the TFT array substrate is exposed without a mask,by also exposing the photoresist provided on the lower pad 15 to remove.The gate insulating film 16 provided on the lower pad 15 is thus exposedand removed at a succeeding etching step. Then, the ITO film is formedover the whole surface and is patterned by using the photolithography,thereby forming the ITO pixel electrode 27 and the upper pads 28 and 29(FIG. 14(b)). In this case, the lower pad 15 and the upper pad 28 aredirectly provided in contact with each other and are electricallyconnected.

[0127] Since the photolithographic step of forming the contact hole inthe gate insulating film 16 is not required, a TFT array substrate canbe fabricated by carrying out the photolithographic step three times,that is, using three photomasks, so that a cost can be further reduced.

[0128] As a matter of course, in the same manner as in otherembodiments, it is possible to remove the semiconductor layer 18 and thesemiconductor layer 17 which are protruded beside the source line 20.Therefore, an aperture ratio can be enhanced and the resistance of thesource wiring can be reduced, and furthermore, it is possible toeliminate a drawback that a source-common capacitance is increased.

[0129] While the source line 20 is exposed in the present embodiment, itis a matter of course that the source line 20 can be covered with theITO film in the same manner as in the EMBODIMENT 2.

INDUSTRIAL APPLICABILITY

[0130] By applying the manufacturing method according to the presentinvention, it is possible to remove a semiconductor layer whichprotrudes beside a source line through a manufacturing step using fourphotomasks as in the conventional art or three photomasks which arefewer than those in the conventional art. Consequently, it is possibleto prevent a reduction in an aperture ratio, an increase in theresistance of the source line and an increase in a source-commoncapacitance. Thus, it is possible to manufacture a liquid crystaldisplay of high quality inexpensively in a short time.

[0131] By covering the source line with the ITO film, furthermore, thereaction of the source line and a liquid crystal can be prevented, sothat a degree of freedom in the selection of the material of the sourceline can be enhanced. Moreover, since the ITO film as well as anoriginal source line can also function as the source line, theresistance of the source line can be further increased so that a liquidcrystal display of high quality can be obtained, and furthermore, thepossibility of a disconnection of the source line can be decreased sothat reliability can be enhanced.

1. A method for manufacturing a TFT array substrate in which at least(a) a gate insulating film, (b) a semiconductor layer and (c) a metallayer are sequentially formed in this order of (a), (b) and (c), andusing one resist pattern formed by a photolithography, a part of themetal layer is selectively removed, to form a source line, together withthe semiconductor layer beside the source line, wherein a passivationfilm is formed after the formation of the source line and the removal ofthe semiconductor layer beside the source line, a resist pattern toselectively remove the passivation film is formed on the passivationfilm, and using the resist pattern, the passivation film above thesource line, the passivation film beside the source line and the gateinsulating film beside the source line are removed to, thereby, exposethe semiconductor layer under the source line.
 2. A method formanufacturing a TFT array substrate according to claim 1, wherein aportion protruding beside the source line is removed from the exposedsemiconductor layer under the source line through etching utilizing theresist pattern to selectively remove the passivation film and/or thesource line as a mask.
 3. A method for manufacturing a TFT arraysubstrate according to claim 1, wherein a portion protruding beside thesource line is removed from the exposed semiconductor layer under thesource line through etching utilizing the selectively removedpassivation film and/or the source line as a mask.
 4. A method formanufacturing a TFT array substrate in which at least (a) a gateinsulating film, (b) a semiconductor layer and (c) a metal layer aresequentially formed in this order of (a), (b) and (c), and using oneresist pattern formed by a photolithography, a part of the metal layeris selectively removed, to form a source line, together with thesemiconductor layer beside the source line, wherein no passivation filmis formed after the formation of the source line and the removal of thesemiconductor layer beside the source line.
 5. A method formanufacturing a TFT array substrate in which at least (a) a gateinsulating film, (b) a semiconductor layer and (c) a metal layer aresequentially formed in this order of (a), (b) and (c), and using oneresist pattern formed by a photolithography, a part of the metal layeris selectively removed, to form a source line, together with thesemiconductor layer beside the source line, wherein no passivation filmis formed after the formation of the source line and the removal of thesemiconductor layer beside the source line, so that the source line andthe semiconductor layer under the source line remain exposed, and aportion protruding beside the source line is removed from the exposedsemiconductor layer under the source line through etching utilizing thesource line as a mask.
 6. A method for manufacturing a TFT arraysubstrate according to claim 1, 2, 3, 4 or 5, wherein a ITO film isfurther formed, and through patterning to selectively remove the ITOfilm, the ITO film on the source line is left to form the ITO filmcovering the source line.
 7. A method for manufacturing a TFT arraysubstrate in which at least (a) a gate insulating film, (b) a firstsemiconductor layer, (c) a second semiconductor layer and (d) a metallayer are sequentially formed in this order of (a), (b), (c) and (d),and a resist pattern comprising a region in which photoresist isremoved, a region in which photoresist has a small thickness and aregion in which photoresist has a great thickness is further formed bymeans of a photolithography, wherein the metal layer, the secondsemiconductor layer and the first semiconductor layer are removed in theregion in which photoresist is removed, the metal layer and the secondsemiconductor layer are removed in the region in which photoresist has asmall thickness, and the metal layer, the second semiconductor layer andthe first semiconductor layer are left remained in the region in whichphotoresist has a great thickness to form a source line with the metallayer left remained, and wherein a region adjacent to the source line isthe region in which photoresist has a small thickness, so that the metallayer and the second semiconductor layer are removed and the firstsemiconductor layer is left remained.
 8. A method for manufacturing aTFT array substrate in which at least (a) a gate insulating film, (b) afirst semiconductor layer, (c) a second semiconductor layer and (d) ametal layer are sequentially formed in this order of (a), (b), (c) and(d), and a resist pattern comprising a region in which photoresist isremoved, a region in which photoresist has a small thickness and aregion in which photoresist has a great thickness is further formed bymeans of a photolithography, wherein the metal layer, the secondsemiconductor layer and the first semiconductor layer are removed in theregion in which photoresist is removed, the metal layer and the secondsemiconductor layer are removed in the region in which photoresist has asmall thickness, and the metal layer, the second semiconductor layer andthe first semiconductor layer are left remained in the region in whichphotoresist has a great thickness to form a source line with the metallayer left remained, wherein a region adjacent to the source line is theregion in which photoresist has a small thickness, so that the metallayer and the second semiconductor layer are removed and the firstsemiconductor layer is left remained, and wherein a passivation film isformed aftre removal of the photoresist, a resist pattern to selectivelyremove the passivation film is formed on the passivation film, and usingthe resist pattern, the passivation film above the source line and thepassivation film beside the source line are removed to, thereby, exposethe second and first semiconductor layers under the source line.
 9. Amethod for manufacturing a TFT array substrate according to claim 8,wherein a portion protruding beside the source line is removed from theexposed second and first semiconductor layers under the source linethrough etching utilizing the resist pattern to selectively remove thepassivation film and/or the source line as a mask.
 10. A method formanufacturing a TFT array substrate according to claim 8, wherein aportion protruding beside the source line is removed from the exposedsecond and first semiconductor layers under the source line throughetching utilizing the selectively removed passivation film and/or thesource line as a mask.
 11. A method for manufacturing a TFT arraysubstrate in which at least (a) a gate insulating film, (b) a firstsemiconductor layer, (c) a second semiconductor layer and (d) a metallayer are sequentially formed in this order of (a), (b), (c) and (d),and a resist pattern comprising a region in which photoresist isremoved, a region in which photoresist has a small thickness and aregion in which photoresist has a great thickness is further formed bymeans of a photolithography, wherein the metal layer, the secondsemiconductor layer and the first semiconductor layer are removed in theregion in which photoresist is removed, the metal layer and the secondsemiconductor layer are removed in the region in which photoresist has asmall thickness, and the metal layer, the second semiconductor layer andthe first semiconductor layer are left remained in the region in whichphotoresist has a great thickness to form a source line with the metallayer left remained, wherein a region adjacent to the source line is theregion in which photoresist has a small thickness, so that the metallayer and the second semiconductor layer are removed and the firstsemiconductor layer is left remained, and wherein no passivation film isformed after removal of the resist pattern.
 12. A method formanufacturing a TFT array substrate in which at least (a) a gateinsulating film, (b) a first semiconductor layer, (c) a secondsemiconductor layer and (d) a metal layer are sequentially formed inthis order of (a), (b), (c) and (d), and a resist pattern comprising aregion in which photoresist is removed, a region in which photoresisthas a small thickness and a region in which photoresist has a greatthickness is further formed by means of a photolithography, wherein themetal layer, the second semiconductor layer and the first semiconductorlayer are removed in the region in which photoresist is removed, themetal layer and the second semiconductor layer are removed in the regionin which photoresist has a small thickness, and the metal layer, thesecond semiconductor layer and the first semiconductor layer are leftremained in the region in which photoresist has a great thickness toform a source line with the metal layer left remained, wherein a regionadjacent to the source line is the region in which photoresist has asmall thickness, so that the metal layer and the second semiconductorlayer are removed and the first semiconductor layer is left remained,and wherein no passivation film is formed after removal of the resistpattern, and a portion protruding beside the source line is removed fromthe second and first semiconductor layers under the source line throughetching utilizing the source line as a mask.
 13. A method formanufacturing a TFT array substrate according to claim 7, 8, 9, 10, 11or 12, wherein a ITO film is further formed, and through patterning toselectively remove the ITO film, the ITO film on the source line is leftto form the ITO film covering the source line.
 14. A method formanufacturing a TFT array substrate according to claim 12, wherein aphotoresist on a lower electrode pad at the end of the gate line isremoved through a peripheral exposing step in which no mask is used, sothat a part of the gate insulating film is removed by etching to exposethe lower electrode pad at the end of the gate line.